Audio Electronics
Electronic Modules
Electronic Modules for Audio is a system of stackable perf board
circuit modules using a Samtec ESQ-106-44-T-S stacking pin/socket
connector for a shared power and signal bus. The perf board is on
0.1" centers, one inch square, and the connectors provide for 0.735"
clearance between boards. The modules consist of simple, high
quality, low-cost audio functions, and other signal functions and
instrumentation. The modules can be enclosed in a variety of
enclosures.
Microphone preamp - this module includes RCA connectors for microphone
input and output, and a transistor preamp circuit with thumbwheel gain
to raise a microphone signal to line level.
Microphone balancing transformer - this module contains a micro stereo
jack configured for balanced microphone input and a transformer feeding
a microphone preamp module via the signal bus.
Mixer - this module includes a transistor amplifier circuit with a
thumbwheel output level and an RCA connector for line output. The
amplifier input accepts microphone preamp outputs connected to a
mixing bus on the Samtec stacking connector.
Level Meter - this module provides a level meter for one of the bus
signals. Shorting blocks are used to select the bus channel.
Samtec ESQ-106-14-T-S : 50 x $ 0.478 + $ 9.50 = $ 33.40
In audio signal chains, there can exist transducers, amplifiers and
processors, and interconnecting cables.
Regarding the impedance switches on some audio preamps,
impedance-matching is not beneficial in audio signal chains, because
the concern is voltage transfer, not power transfer, however, an input
fed from a long line should be lower impedance to prevent line
capacitance from excessively limiting signal bandwidth (RC lowpass
filter effect).
Rane:
Impedance match passive components (transformers) to maintain "unity
gain" but no need/desire to impedance match active components.
On high-Z vs low-Z preamps:
Maxim:
Bipolar input stage has high current noise thus better s/n ratio with a
low-Z (high current) source.
JFET input stage has high voltage noise thus better s/n
ratio with a high-Z (high voltage) source.
Tutorial DSP-based testing of analog and mixed-signal circuits:
To evaluate voltage noise we use a low impedance input network so the
developed current dominates the internal current noise.
To evaluate current noise we use a high impedance input network so the
developed voltage dominate the internal voltage noise.
But what about impedance bridging?
Whirlwind:
Hi-Z sources generate hi V so better Voltage S/N ratio but Hi-Z
sources/sinks create with excessive line capacitance a lowpass filter
that limits the audio bandwidth. Also Hi-Z is more vulnerable to
outside interference. So if the line has high capacitance, and/or
there is a lot of external interference fields, and the amp stages are
low noise, low-Z source and sink impedances will result in less overall
noise.
A sink impedance should be significantly higher than the source
impedance to prevent loading which reduces S/N ratio.
However with long lines a higher sink impedance can interact with
line capacitance to form a lowpass filter that cuts into signal
bandwidth.
---------\ <- Hi source Z gens hi sig level but too hi relative to sink Z causes sig to sag
\ <- Hi source/sink Z can setup filter with line cap that cuts into audio bandwidth
_____________ <- Hi source Z can raise noise floor from outside interference
Instrument/Recorder
Interface Specs
Powerbook sound line in has the following electrical characteristics:
■ maximum input signal amplitude 2 Vrms (5.65 Vpp), +8 dbu peak
■ input impedance at least 47 kilohms
■ channel separation greater than 60 dB
■ recommended source impedance 2 kilohms or less
■ ground noise rejection greater than 40 dB
■ frequency response 5 Hz to 20 kHz, +0.0, –0.5 dB
■ distortion below –80 dB
■ signal to noise ratio (SNR) greater than 90 dB (unweighted)
powerbook line in has dc blocking cap - tested with battery
powerbook line in noise from digital circuits
open ended -68 db
2.7k resistor -78 db
short circuit - 90 db
powerbook audio in apparently has 3dB greater range than audio
out. I sent full scale out back in, adjusting alsamixer
PCM1 level to 61 where any increase failed to raise the input value.
Since the test signal was full scale, this means PCM1 level 61 is unity
gain. The input measurement was -3dB. Given the spec sheet
says output is 2v p-p max, the input must be 2.82v p-p max or 2 vrms
max. (verified from powermac G4 docs that this is the standard
design) This means I don't need more than 2.82v p-p out of the
preamp so I can have a higher gain.
instrument impedance:
dan 5k, bass 30k , wash 50k, mic 50k
instrument peak level direct into powerbook:
dan -18db, bass -20 db, wash -9db, mic -30 db
JFET Amplifier
A junction field effect transistor,
JFET, has a gate, drain
and source
pins and operates in depletion-mode, meaning a negative gate-source
voltage, Vgs, causes current, Id, to flow between drain and
source. An n-channel JFET is operated with drain-source voltage
Vds > 0. See figure below. When Vds is less than its
saturation voltage, the device is in linear mode and its d-s channel
behaves like a variable resistor controlled by Vgs. When Vds is greater
than its saturation voltage the device is in saturation mode and its
d-s channel behaves like a constant
current source controlled by Vgs, independent of Vds, and useful
as a signal amplifier. JFETs have very high gate
impedance and very low gate current, thus JFETs present minimal
loads on driving circuits and require less bias current than bipolar
transistors. As audio amplifiers, JFETs overdrive with pleasing
harmonics, similar to vacuum
tubes. Disadvantages include wide parameter variation among
transistors, limited control over gain, and relatively high output
impedance.
A single transistor JFET amplifier is usually configured as
common source
which inverts the signal. The simplest approach to
biasing a JFET common source amplifier is
self-biasing, in which the gate quiescent (DC) voltage level is
tied to ground with a high value resistor Rg
typically in the megaohms (1). The
signal input is applied at the gate.
A
resistor Rs between the JFET source and ground sets Vs quiescent level,
Vsq,
and Id quiescent level, Idq. Rs causes Id to raise the source
voltage Vs > 0, maintaining Vgs < 0 and the JFET in saturation
mode. As the input signal Vg is raised/lowered about ground, Vs
moves toward its upper/lower limits (Idss*Rs and ground), seeking to
minimize Vgs. The
JFET drain voltage Vd is the amplifier output signal. A
resistor Rd between supply voltage Vdd and the drain sets Vd quiescent
level, Vdq.
To find Rs and Rd, first measure Idss (Id saturation current, where Vgs
= 0) and Vgsc (Vgs
cutoff voltage, where Id = 0). Idss is measured with
an ammeter connected
between Vdd and JFET drain, with gate and source connected to
ground. A large value resistor R to make Id very small is then
inserted between source and ground
and Vgsc is measured with a voltmeter. There is normally a
wide variance in the Idss and Vgsc (and transconductance)
characeristics among individual
JFETs. Matching may be required.
Id has upper/lower limits Idss and zero. Vgs has upper/lower limits
zero and Vgsc. The JFET saturation approximation is Id = Idss *
(1
–
Vgs/Vgsc)**2, and Vgs =
Vgsc*(1-sqrt(Id/Idss)). Different values of Vgsq or Idq are tried
to
best satisfy the various design critera. One such criterion may
be to ensure Idss*Rs is low enough to accommodate the output signal
headroom requirement. Distortion is minimized
when Idq is closer to Idss [2]. By Ohm's law, Rs = Vsq/Idq, or
-Vgsq/Idq,
since Vgq = 0 in the common source configuration. It would seem
reasonable to set Vdq to the midpoint
between Vdd and Idss*Rs, the upper limit for Vs, so Vdq =
(Vdd+Idss*Rs)/2, and Rd = (Vdd-Vdq)/Idq. But gain, headroom and
distortion considerations may require a different Vdq.
Voltage gain Av = -Rd/(Rs+1/gm) (2),
where transconductance gm (>0 mhos) =
d(Id)/d(Vgs), which may be measured, is available from JFET spec
sheet. gm = (-2*Idss/Vgsc)*(1
- Vgsq/Vgsc) [1]. Av is therefore controlled by both the
selection of
the JFET and the resistor values.
To achieve
higher
Av for AC signals, one may connect a capacitor Cs || Rs, which
preserves the DC biasing
function of Rs while shorting out
Rs for AC signals: Avacs = -gm*Rd. Cs and Rd ||
Rs create a highpass filter with knee frequency Fn = 1/(2*pi*R*C)
that should be set below 20 Hz for audio. A variable resistor Rv
between Cs and ground allows varying the AC gain Avacv =
-Rd/((Rs||Rv) + 1/gm). A reverse audio taper
potentiometer with the
higher resistance per unit travel at the counterclockwise end gives
an
approximately linear gain
increase as the pot's wiper attached to the capacitor is turned
clockwise
toward the end attached to ground. The width of the gain
range may be increased with Vgsq biased closer to Vgsc, if the
input/output signal voltage ranges remain properly
accommodated/provided. Setting higher |Vgsq| and lower Vdq
produce greater gain. Vdq should be set to Vdd -
(Vdd/(Avmin+1))/2. JFETs with larger Idss and smaller |Vgsc|
produce greater gain, but larger |Vgsc| produces a wider gain
range.
An output coupling capacitor Co may be needed to prevent the load
resistance Rl
from altering the quiescent level of Vd. This capacitor and Rl
create a
highpass filter with knee frequency Fn = 1/(2*pi*Rl*Co) that should be
set below 20 Hz for audio.
Vdd | .. --- Vdd
| | . .
# Rd | . .
| Co | . . Vd
|------+||---Vo | . .
d|-- Vd | . . . --- Vdq
Vg---> g| | . .
s|-- Vs Cs | . .
|------+||-- | . .
| | | ..
# Rs # Rv | ** Vs --- Idss*Rs
| | | * / \ * * --- Vsq
Gnd Gnd |____/____\__**____ --- 0V
| \ /
| \__/ Vg --- Vgsc
|
(1) Rg may be omitted if the driving circuit is directly, not
capacitively, coupled and holds the DC signal level to ground.
(2) If significant loading by load resistance Rl, use Rl||Rd in place
of Rd.
[1]
Kuhn
- JFET
Basics
[2]
Kuhn -
JFET Supplemental (scroll down)
[3]
UCB
labs - JFETS I
[4]
UCB
labs - JFETS II
[5]
FET
Amp
Designing
[6]
JFET - Wikipedia
Computer Stereo Audio
Line-in Application
For use with high and low
impedance dynamic microphones and musical instrument transducers with
short cables, to computer line-in for recording, the preamp consists of
a pair of JFET common-source
amplifiers as described above with single-ended (unbalanced)
1/4" mono input jacks, a stereo 1/8" output jack, and a USB B connector
for 5V power. The output is limited by JFET staturation to 2.82
vpp, the
industry standard line-in voltage. The preamp gain should be set
for the loudest output signal to be near 2.82 vpp, or full scale
according to the recording level meters. The channel gain range
is +6dB to +15dB.
The input jacks are
shunting types to
shunt an unused channel's input to ground so an input
resistor is unneeded. The first channel output is fed
internally to the second channel
input shunt through a voltage divider. Leaving the second channel
input unplugged, and its gain at minimum, the second channel becomes a
unity gain inverting follower of the first channel, turning the stereo
connection into a balanced line. The first channel gain may be
set for a
full scale output signal according to the record level meter and then
both channels recorded. After digitizing, the tracks may be
subtracted/halved into one track to reject
common mode noise
picked up between the preamp and the analog-digital converters.
On the powerbook5,3 this cut noise by 6 dB bringing noise down to
90dB. In this configuration, the second channel gain may be
turned up to obtain a total of 24dB gain and possibly some harmonious
distortion at the second channel
output. Two separate instruments may be recorded at the same time
using both input jacks but without the noise rejection feature and gain
limited to 15dB max. The second channel output has a
resistor to ground matching the total
resistance of the voltage divider to match loads/levels on
both channels.
A 150 Ohm, 100 uF RC lowpass filter on Vdd was needed to
filter out a higher freq hum from the powerbook Vdd. Leaving the
USB ground pin disconnected (using the audio ground for power return)
improved this filtering further but it had to be connected back up for
use
with a USB wall-wart. The wall wart's 60 Hz hum was significant
so a 56 Ohm resistor wasn needed in line with the ground. The
powerpook5,3 was still creating a 3 sec interval transient noise
raising the noise floor 10dB so the RC filter capacitance
had to be increased to 200 uF, dropping the transient noise down
3dB.
Vdd powers both preamps Vdd -----+----#------ Pvdd
| | 150
16200 # Rd 4.7uF _+_ +5v USB conn
| Co === 2x100uF
J201 |------+||---Vo |
d|-- Vd Gnd -----+----#------ Pgnd
Vg---> g| 56
s|-- Vs Cs 100uF
|------+||-,
| | 50k ______
2640 # Rs Rv # Rev Log | |
| | || \/-----------| L |------+----------;
Gnd Gnd || ^--; |______| | |
|------| # 34000 |
channel preamp Gnd ;----------------| '--- ||
| # 34000 | 3.5mm stereo jack
2 1/4" phone jacks | | ;--- ||
| ______ Gnd | |
| | | | Gnd
|| \/--------)--| R |------+----------'
|| ^-------' |______| |
| # 64900
Gnd |
Gnd
Preamp Development Notes
Multichannel
Audio Digitizer
A multi-channel audio digitizer is needed to record live bands and for
recording drum kits in the studio. This project utilizes the JFET
amplifier and high speed transistors to digitize
multiple audio channels. As of Nov 2009 this project is in the
research stage. The idea is to minimize full costs, including
embedded costs and economic costs, and release proprietary control of
most of the design and fabrication to the public domain. This
approach relies on the host computer to perform as much of the work as
possible on the premise that the computer CPU resource is
underutilized, generally, and during recording, and thus available for
processing the
digitized signals. In cases where there isn't enough CPU
available for the processing during record, it's also possible to store
the raw
data on disk and perform the post-processing phase later, offline.
It's therefore conceivable that the digitizer hardware may consist of
as little as four transistors, and a few passive components, per audio
input channel, the first
transistor being a JFET amplifier, the second being a high-speed
sample-and-hold, the third being a high speed
comparator, and the fourth being a high-speed multiplexor switch.
The
amplifier would gain up a single-ended microphone signal 10 to 20dB to
raise it over the digitizing noise. The sample-and-hold would
provide a stable voltage level in the sampling interval for the
comparator which would compare it with the value in the previous
interval stored in a small
capacitor. The difference would be represented by a binary value
of either 1 or
0, indicating an increasing or decreasing voltage. The channel
multiplexer would allow a single bitstream on the computer firewire
input to
sample multiple audio input channels.
The computer CPU would de-multiplex the channels and perform
delta-sigma sample rate conversion on each. It's possible
therefore that to make a good quality eight channel audio digitizer
would require as few as 32 discrete transistors (plus a clock/counter),
for as low as $30 for the whole hardware package.
Copyright (c)
2009
Robert Drury
Permission is granted to copy, distribute and/or modify this document
under the terms of the GNU Free Documentation License, Version 1.2
or any later version published by the Free Software Foundation;
with no Invariant Sections, no Front-Cover Texts, and no Back-Cover
Texts.
See "GNU
Free Documentation License".
Disclaimer: This information may contain inaccuracies and is
provided
without warranty. Safety first when working with high
temperatures,
pressures, potentials, speeds, energies, various
tools and materials.
that